Data Sheet

AD5547/AD5557

Rev. D | Page 9 of 20

Pin No.

Mnemonic

Function

23

RS

Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.

Signal level must be ≤V

24 to 28,

30 to 38

D13 to D0

Digital Input Data Bits D13 to D0. Signal level must be ≤V

29

VDD

Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.

Table 5. Address Decoder Pins

A1

A0

Output Update

0

0

DAC A

0

1

None

1

0

DAC A and DAC B

1

1

DAC B

Table 6. Control Inputs

RS

WR

LDAC

Register Operation

0

X

X

Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1.

1

0

0

Load the input register with data bits.

1

1

1

Load the DAC register with the contents of the input register.

1

0

1

The input and DAC registers are transparent.

1

When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register

on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse.

1

1

0

No register operation.