IC-MU datasheet(21/59 Pages) ICHAUS

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iC-MU OFF-AXIS NONIUS ENCODER

WITH INTEGRATED HALL SENSORS

Rev B1, Page 21/59

ANALOG SIGNAL CONDITIONING FLOW: x = M,N

For the purpose of signal conditioning iC-MU has sev-

eral settings that make internal reference values and

the ampliﬁed Hall voltages of the individual sensors ac-

cessible at the outer pins of PORT B for measurement.

This allows the settings of the ampliﬁer (GC_x, GF_x),

the amplitude ratio of cosine to sine signal (GX_x), and

the offset (VOSS_x , VOSC_x) and phase (PH_x) of

the master (x = M) and nonius tracks (x = N) to be di-

rectly observed on the oscilloscope.

Test mode can be programmed using register TEST

(address 0x18). The individual test modes are listed in

Table 22 and 23.

N.B.:

MODEB must be set to 0x0 before selecting a test

mode.

Test Mode output signals

Modus

TEST

Pin PB0

Pin PB1

Pin PB2

Pin MTC

Normal

0x00

Analog REF

0x1F

VREF

VBG

IBM

Digital CLK

0x26

CLK

Table 22: Test modes for signal conditioning

1. Conditioning the BIAS current

First of all, the internal bias is set.

The BIAS cur-

rent is adjustable in the range of -40 % to +35% to

compensate variations of this current and thus differ-

ences in characteristics between different iC-MU (e.g.

due to manufacturing variations). The nominal value

of 200 µA is measured as a short-circuit current at pin

PB2 referenced to VNA in test mode 0x1F.

Additionally various internal reference voltages are

available for measuring in this test mode. VREF corre-

sponds to half the supply voltage (typically 2.5 V) and

is used as a reference voltage for the hall sensor sig-

nals. VBG is the internal bandgap reference (1.25 V)

Alternatively the frequency at Pin MTC can be adjusted

to 380 kHz using register value CIBM in test mode

0x26, if an analog measuring of the current is not pos-

sible.

Test mode output signals

Modus

TEST

Pin PB0

Pin PB1

Pin PB2

Pin PB3

Normal

0x00

Analog Master

0x01

PSM

NSM

PCM

NCM

Analog CNV_M

0x03

PSIN_M

NSIN_M

PCOS_M

NCOS_M

Analog Nonius

0x11

PSN

NSN

PCN

NCN

Analog CNV_N

0x13

PSIN_N

NSIN_N

PCOS_N

NCOS_N

Table 23: Testmodes and available output signals

The output signals of the signal path are available as

differential signals with a mean voltage of half the sup-

ply voltage and can be selected for output according to

Table 23.

2. Positioning of the sensor

Next, the sensor should be adjusted in relation to the

magnetic code carrier. The value of MPC (Table 48)

has to be selected according to the magnetic code car-

rier. The register values for VOSS_x, VOSC_x, GX_x

and PH_x are set to 0. The chip position will now be

displaced radially to the magnetic code carrier until the

phase shift between the sine and cosine is 90°.

Depending on the mounting of the system it may be

necessary to displace iC-MU tangentially to the mag-

netic code carrier to adjust the amplitude between the

sine and cosine signals.

A ﬁne adjustment of the analog signals is made with

the registers described in the chapter SIGNAL CONDI-

TIONING FOR MASTER AND NONIUS CHANNELS

page 19.

The adjustment should be made in the order:

1. phase

2. amplitude

3. offset

3.a Test modes analog master and analog nonius

In these test modes the ampliﬁed, conditioned signals

are presented to port B. These signals can be charged

with a maximum of 1 mA and should not exceed a dif-

ferential voltage of 0.5 Vpp.

3.b Test mode CNV_x

In this test mode the sensor signals are present at port

B as they are internally for further processing on the

interpolator. The achievable interpolation accuracy is

determined by the quality of signals PSIN_x/NSIN_x

and PCOS_x/NCOS_x and can be inﬂuenced in this

test mode by adjustment of the gain, amplitude ratio,

offset, and phase. The signals must be tapped at high

impedance.

4. Trackoffset SPON

After the analog adjustment of the master and non-

ius track the absolute system must be electrically cal-

ibrated for maximum adjustment tolerance. See page

36 ff.

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