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MD3872DB1

Supertex inc.

www.supertex.com

Doc.# DSDB-MD3872DB1

A051713

MD3872DB1 Hardware Design

The eight channels of MD3872 LNA inputs are connected

to eight input signal SMA connectors via a transmit/receive

switch circuit, TRSW, as shown below. The T/R switches

used here are two Supertex MD0105s, 4-channel, ±130V,

15Ω devices. They are two-terminal devices. A pair of back-

to-back diodes, D24, are present to protect the LNA input

circuit from high-voltage transmission pulses and voltage

spikes from the transducer and long cable lines. The T/R

switch provides a low on-resistance (normal ON state) at

receiving time and a high impedance (OFF state) when high

voltage pulses are present. These input circuits enable the

user to directly evaluate their echo signal processing using

the MD3872 front-end receiver in their ultrasound system.

The trans impedance LNA gain setting of resistor R

is 249Ω when LNA SW is OFF. Because the R

is 590Ω, that means when LNA SW is ON, the effective

resistance is R

for the LNA input impedance calculation and LNA SW SPI

control bits.

In order to simplify testing of the CW cross-point switch

current source outputs, one channel CW1± pins have been

connected to a tightly coupled, center-taped, wind-band RF

transformer T2 and to an SMA connector J21.

There is an SPI serially interfaced 12-bit precision DAC on

board for quick evaluation of the TGC function of MD3872.

It can generate 0 to 1.8V with 0.44mV step resolution. R45

and R34 form a simple DAC output voltage-divider file that

scales the TGC signal. The Gain-Scaling Control pin GSC

has been pulled up to 1.8V AVDD by R30, which means that

GSC is set to 50dB/V TGC gain on this demoboard. One

can easily install a proper value on the resistor R36 (open as

default) to reset the TGC gain. Note that the VGSC minimum

voltage is 1.44V, which sets the TGC gain to about 66dB/V.

Although there is a built-in ADC reference voltage source

in MD3872, for evaluating the external referencing option,

there is an additional on-board precision 1.024V reference

device, U9, which can work with the jumper J24 to select the

internal or external reference. When selecting the external

reference, the EXT jumper should be Hi.

The MD3872 reference pins’ top and bottom voltages of

the ADC are not only for testing the voltages, but also for

bypassing capacitors differentially (C135 & C146) as well

as common-mode to ground (C153 & C154). When the IC

is working at 40 or 50MSPS speeds, all eight channels of

the ADl need a very large peak current into or out of the

reference voltage pins. It is important to keep the ADC

reference filtered as the current ripples especially in the

differential mode.

Users should leave the EBC pin disconnected. It is for

manufacturer testing only. The AVDD pins are connected to

a low noise +1.8V isolated power supply. The AVDD supply

pins need to be thoroughly decoupled to make sure that LNA

is working a low EMI/RFI conditions.

All digital outputs, especially the eight channels of LVDS,

working at 480bit/s data speed consumes a large amount of

power. One can slightly increase the DVDD voltage by +1.90

to 1.95V for better LVDS output waveforms at 300MHz DCLK

when 50MSPS maximum sampling rate becomes necessary.

The DVDD power rail is supplied by a separate LDO U11.

These AVDD and DVDD regulators feedback sense pins are

directly connected to the ferrite bead down stream and the

corresponding power supply pins separately. This method

will provide accurate voltage and lower noise.

The MD3872 +3.3V CVDD it connected to a CW cross point

switch circuit. Foe those applications that do not need CW

signals, one can simply connect the CVDD to 1.8 as well.

PCB Board Design

The MD3872 sampling clock input signals are 40 or 50MHz

from two low-jitter LVDS crystal oscillators, via a shared

differential-clock bus, which is terminated with a 100Ω

differential load resistor. The bus lines must be comprised

of two closely coupled, length-matched, 50Ω impedances to

ground. The 100Ω resistor load must be placed very close to

the MD3872 CLK± pins.

Besides the clock input pins, all the other pairs of LVDS

output pins to FPGA de-serialized input pairs also need to

be the same type of transmission lines that are designed

on the PCB. The termination resistors, however, are not

needed due to the built-in LVDS termination feature of the

Spartan-6 FPGA circuit. But length-matching of the LVDS

lines is very critical to the ADC output data pairs OUTn± vs.

DCLK± and FCLK± pairs. Precision trace line impedance-

control by a PCB fabrication house is highly recommended,

although MD3872 has built-in programmable LVDS output

skew alignment features.

The most important thing about the PCB design for the

MD3872 receiver front-end IC, besides the line impedance

control, is the ground plane selection and ground integrity.

Supertex recommends that if MD3872 is on the top layer

of the PCB stack, then the ground must be the second

layer. The center-bottom of the IC’s thermal pad should be

well connected to the ground plane electrically as well as

thermally. The vias on the thermal pads should use about

a 0.3mm diameter drill for the through hole matrices with

1.0mm pitch. However, do not let the pad electrically con-

nect to the other layers of the PCB stack, even if they are

named as GND , but thermally it can connect to as many