A5841SLW datasheet(5/8 Pages) ALLEGRO

5 / 8 page

5841 AND 5842

8-BIT SERIAL-INPUT,

LATCHED DRIVERS

www.allegromicro.com

TRUTH TABLE

Serial

Shift Register Contents

Serial

Latch Contents

Output Contents

Data

Clock

Data

Strobe

Output

Input

Input I1

.............. I8

Output

Input

.............. I8

Enable

I1 I2 I3 .............. I8

R1 R2 .............. R7

XR1 R2 R3 .............. R8

.............. X

R1 R2 R3 .............. R8

P1 P2 P3 .............. P8

HP1 P2 P3 .............. P8

LP1 P2 P3 .............. P8

.............. X

.............. H

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

TYPICAL APPLICATION

RELAY/SOLENOID DRIVER

Using Split Supply

Dwg. No. A-12,547

UCN5842A

The products described here are manufactured

under one or more U.S. patents or U.S. patents

pending.

Allegro MicroSystems, Inc. reserves the right to

make, from time to time, such departures from the detail

specifications as may be required to permit improve-

ments in the performance, reliability, or

manufacturability of its products. Before placing an

order, the user is cautioned to verify that the informa-

tion being relied upon is current.

Allegro products are not authorized for use as

critical components in life-support devices or systems

without express written approval.

The information included herein is believed to be

accurate and reliable. However, Allegro

MicroSystems, Inc. assumes no responsibility for its

use; nor for any infringement of patents or other rights

of third parties which may result from its use.

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