MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE

MP2932 Rev.1.02

www.MonolithicPower.com

13

4/30/2012

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© 2012 MPS. All Rights Reserved.

Soft-Start

MP2932 has 4 periods during soft-start as

shown in Figure 7. After VCC, EN_VTT and

EN_PWR reach their POR/enable thresholds,

1.36ms. After the delay period, the VR will

begin first soft-start ramp until the output

voltage reaches 1.1V. Then, the controller will

regulate the VR voltage at 1.1V for another

reads the ID signals. If the ID code is valid,

MP2932 will initiate the second soft-start ramp

until the voltage reaches the ID voltage minus

offset voltage.

500us/DIV

EN_VTT

VR_RDY

1.1V

Figure 7—Soft-Start Waveforms

The soft-start time is the sum of the 4 periods,

as shown in Equation (11):

d4

t

d3

t

d2

t

d1

t

SS

t









(11)

fixed 85µs plus the time to obtain valid ID

voltage. If the ID is valid before the output

reaches the 1.1V, the minimum time to validate

the ID input is 500ns. Therefore the minimum

DAC voltage change at 6.25mV per step. The

time for each step is determined by the

frequency of the soft-start oscillator which is

be calculated based on Equations (12) and (13):

(us)

6.25

SS

R

1.1

d2

t

25

3

2









(12)





(us)

6.25

SS

R

1.1

VID

V

d4

t

25

3

2











(13)

For example, when ID is set to 1.5V and the

After the DAC voltage reaches the final ID

setting, VR_RDY will be set to high with the

VR_RDY Signal

The VR_RDY pin is an open-drain logic output.

It is pulled low during shutdown and releases

high after a successful soft-start. VR_RDY will

be pulled low when an under-voltage or over-

voltage condition is detected, or the controller is

disabled by a reset from EN_PWR, EN_VTT,

POR, or ID OFF-code.

Under-voltage Detection

The under-voltage threshold is set at 50% of

the ID code. When the output voltage at VSEN

is below the under-voltage threshold, VR_RDY

is pulled low.

Over-voltage Protection (OVP)

Regardless of the VR being enabled or not, the

MP2932 OVP circuit will be active after its POR.

The OVP thresholds are different at different

operation conditions. When VR is not enabled

the OVP threshold is 1.275V. Once the

controller detects valid ID input, the OVP trip

point will be changed to DAC + 175mV.

SOFT-START, FAULT

AND CONTROL LOGIC

50%

DAC

VDIFF

VID + 0.175V

85uA

I

VR_RDY

OC

UV

OV

AVG

Figure 8—VR_RDY and Protection Circuitry