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AGLP030 Scheda tecnica(PDF) 59 Page - Microsemi Corporation |
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AGLP030 Scheda tecnica(HTML) 59 Page - Microsemi Corporation |
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59 / 134 page  IGLOO PLUS Low Power Flash FPGAs Revision 16 2-45 Input Register Timing Characteristics 1.5 V DC Core Voltage Figure 2-14 • Input Register Timing Diagram 50% Clear Out_1 CLK Data Preset 50% t ISUD t IHD 50% 50% t ICLKQ 1 0 t IRECPRE t IREMPRE t IRECCLR t IREMCLR t IWCLR t IWPRE t IPRE2Q t ICLR2Q t ICKMPWH tICKMPWL 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% 50% Table 2-74 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.41 ns tISUD Data Setup Time for the Input Data Register 0.32 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.57 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.57 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width High for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width Low for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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