AX2000 datasheet(74/262 Pages) MICROSEMI

Il numero della parte	AX2000

Spiegazioni elettronici	Axcelerator Family FPGAs

PDF	262 Pages

Scroll/Zoom	100%

Produttore elettronici	MICROSEMI [Microsemi Corporation]

Homepage	http://www.microsemi.com

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Detailed Specifications

2- 60

R e v i sio n 1 8

Buffer Module

Introduction

An additional resource inside each SuperCluster is the Buffer (B) module (Figure 1-4 on page 1-3). When

a fanout constraint is applied to a design, the synthesis tool inserts buffers as needed. The buffer module

has been added to the AX architecture to avoid logic duplication resulting from the hard fanout

constraints. The router utilizes this logic resource to save area and reduce loading and delays on

medium-to-high-fanout nets.

Timing Models and Waveforms

Timing Characteristics

Figure 2-33 • Buffer Module Timing Model

Figure 2-34 • Buffer Module Waveform

Table 2-64 • Buffer Module

Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C

–2 Speed

–1 Speed

Std Speed

Parameter

Description

Min.

Max.

Min.

Max.

Min.

Max.

Units

Buffer Module Propagation Delays

tBFPD

Any input to output Y

0.12

0.14

0.16

OUT

GND

50%

GND

VCCA

tBFPD

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