AM53CF96JC datasheet(30/76 Pages) AMD

30 / 76 page

P R E L I M I N A R Y

AMD

Am53CF94/Am53CF96

the PERE bit is reset and bad parity occurs it is not de-

tected and no action is taken.

CNTLREG1 – Bit 3 – STE – Self Test Enable

The STE bit is for test use only. When the STE bit is set

the device is placed in a test mode which enables the

device to access the test register at address 0AH. To re-

set this bit and to resume normal operation the device

must be issued a hard or soft reset.

CNTLREG1 – Bit 2:0 – CID 2:0 – Chip ID 2:0

The Chip ID 2:0 bits specify the binary coded value of

the device ID on the SCSI bus. The device will arbitrate

with this ID and will respond to Selection or Reselection

to this ID. At power-up the state of these bit are unde-

fined. These bits are not affected by hard or soft reset.

Clock Factor Register (09H) Write

Clock Factor Register

CLKFREG

Address: 09H

Type: Write

7654

210

RES

CLKF2

CLKF1

CLKF0

xxxxx

Reserved

Clock Factor 2:0

Reserved

17348B-29

The Clock Factor Register (CLKFREG) must be set to

indicate the input frequency range of the device. This

value is crucial for controlling various timings to meet the

SCSI specification. The value of bits CLKF 2:0 can be

calculated by rounding off the quotient of (Input Clock

Frequency in MHz)/(5 MHz). The device has a fre-

quency range of 10 to 40 MHz.

CLKFREG – Bits 7:3 – RES – Reserved

CLKFREG – Bits 2:0 – CLKF 2:0 – Clock Factor 2:0

The CLKF 2:0 bits specify the binary coded value of the

clock factor. The CLKF 2:0 bits will default to a value of 2

by a hard or soft reset.

Input Clock

CLKF2

CLKF1

CLKF0

Frequency in MHz

10.01 to 15

15.01 to 20

20.01 to 25

25.01 to 30

30.01 to 35

35.01 to 40

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