AM7968-125JC datasheet(93/127 Pages) AMD

Il numero della parte	AM7968-125JC

Spiegazioni elettronici	TAXIchip Integrated Circuits(Transparent Asynchronous Xmitter-Receiver Interface)

PDF	127 Pages

Scroll/Zoom	100%

Produttore elettronici	AMD [Advanced Micro Devices]

Homepage	http://www.amd.com

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AMD

TAXIchip Integrated Circuits Technical Manual

8.2 Receiver Connections

Refer to Figure 8-2.

Grounding SERIN– puts the Receiver in Test Mode. SERIN+ is a single ended 100K

ECL NRZ input.

The X1 pin now becomes the bit rate clock input (bitclk), just like the CLK pin on the

Transmitter.

The CLK pin remains a

byte rate CLK out.

8.3 Timing Relationships in Test Mode

The timing parameters in Test Mode are similar to the parameters in standard mode.

Propagation delay values remain the same, however bit time relationships are now

calculated with respect to the new bit times. For example, using a bitclk = 1.0 kHz, which

is a 1 ms period, the byte time t35 = 10 bits x 1 ms = 10 ms. In the same way t37, which is

the CLK falling to STRB rising delay is now [2 (t35/n) + 15 ns] = 2.015 ms. Note that

Setup and Hold times for SERIN to X1 are not specified and must be determined for

each application.

Figure 8-2

Receiver Test Mode Connections

DSTRB

DATA OUT

8, 9, 10

COMMAND OUT

4, 3, 2

VLTN

SERIN+

RESET

CLK

DMS

Clock Recovery

Circuit

Digital or Analog

PLL

Am7969

Normal

Function

CNB

DMS Can Be

Set For 8, 9, or

10-Bit Mode

Normal

Function

SERIN–

IGM

CMD STROBE

DATA STROBE

Single Ended

Input From

Transmitter

Byte Rate CLK Out

CSTRB

12330E-36

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