ST8024LACDR datasheet(22/35 Pages) STMICROELECTRONICS

22 / 35 page

Functional description

ST8024L

22/35

Doc ID 17709 Rev 5

The clock may be applied to the card using the following sequence (see Figure 5):

1. Set RSTIN high.

2. Set CMDVCC low.

3. Reset RSTIN low between t3 and t5; CLK starts at this moment.

4. RST remains low until t5, when RST is enabled to be the copy of RSTIN.

5. After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK

pulses before toggling RST.

If the applied clock is not needed, then CMDVCC may be set low with RSTIN low. In this

case, CLK starts at t3 (minimum 200 ns after the transition on I/O), and after t5, RSTIN may

be set high in order to obtain an “answer to request” (ATR) from the card.

Activation should not be performed with RSTIN held permanently high.

Note:

It is recommended that no control smartcard signals are to be shared with any other

devices. Sharing may result in inadvertent activation or deactivation of the smartcard.

Figure 5.

Activation sequence using RSTIN and CMDVCC

Table 22.

Card presence indicator

OFF

CMDVCC

Indication

Card present

Card not present

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