AP160 datasheet(21/25 Pages) AMICC

21 / 25 page

AP160

Version 0.0

AMIC Technology, Inc.

SERIAL PORT TIMING: SHIFT REGISTER MODE TEST CONDITIONS

The values in this table are valid for VCC = 2.7V to 5.5V and Load Capacitance = 80pF

12MHZ Osc

Variable Oscillator

Symbol

Parameter

Min

Max

Min

Max

Units

XLXL

Serial Port Clock Cycle Time

1.0

CLCL

QVXH

Output Data Setup to Clock Rising Edge

700

CLCL

-133

XHQX

Output Data Hold After Clock Rising Edge

CLCL

-117

XHDX

Input Data Hold After Clock Rising Edge

XHDV

Clock Rising Edge to Input Data Valid

700

CLCL

-133

SHIFT REGISTER MODE TIMING WAVEFORMS

INSTRUCTION

tXLXL

tQVXH

tXHQX

tXHDV

tXHDX

VALID

SET TI

SET RI

ALE

CLOCK

OUTPUT DATA

INPUT DATA

WRITE TO SBUF

CLEAR RI

AC TESTING INPUT/OUTPUT WAVEFORMS

VCC-0.5V

0.45V

0.2 VCC + 0.9V

TEST POINTS

0.2 VCC - 0.1V

Note: 1. AC Inputs during testing are driven at V CC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are

made at V IH min. for a logic 1 and V IL max. for a logic 0.

FLOAT WAVEFORMS

TIMING REFERENCE

POINTS

VLOAD + 0.1V

VLOAD - 0.1V

VLOAD

VOL - 0.1V

VOL + 0.1V

Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin

begins to float when a 100 mV change from the loaded VOH /VOL level occurs.

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