AD7682BCPZ datasheet(8/32 Pages) AD

8 / 32 page

AD7682/AD7689

Data Sheet

Rev. D | Page 8 of 32

VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.

Table 5.

Parameter1

Symbol

Min

Typ

Max

Unit

Conversion Time: CNV Rising Edge to Data Available

tCONV

3.2

μs

Acquisition Time

tACQ

1.8

μs

Time Between Conversions

tCYC

μs

Data Write/Read During Conversion

tDATA

1.2

μs

CNV Pulse Width

tCNVH

SCK Period

tSCK

tDSDO + 2

SCK Low Time

tSCKL

SCK High Time

tSCKH

SCK Falling Edge to Data Remains Valid

tHSDO

SCK Falling Edge to Data Valid Delay

tDSDO

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV Low to SDO D15 MSB Valid

tEN

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV High or Last SCK Falling Edge to SDO High Impedance

tDIS

CNV Low to SCK Rising Edge

tCLSCK

DIN Valid Setup Time from SCK Rising Edge

tSDIN

DIN Valid Hold Time from SCK Rising Edge

tHDIN

1 See

and

for load conditions.

Figure 2

Figure 3

IOL

500µA

IOH

1.4V

TOSDO

50pF

Figure 2. Load Circuit for Digital Interface Timing

30% VIO

70% VIO

2V OR VIO – 0.5V1

0.8V OR 0.5V2

2V OR VIO – 0.5V1

tDELAY

1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

AD7682BCPZ Scheda tecnica(PDF) 8 Page - Analog Devices

AD7682BCPZ Scheda tecnica(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Scheda tecnica Scarica

Link URL