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IO96NDB2V1 Scheda tecnica(PDF) 41 Page - Microsemi Corporation |
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IO96NDB2V1 Scheda tecnica(HTML) 41 Page - Microsemi Corporation |
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41 / 242 page ![]() ProASIC3L Low Power Flash FPGAs Revision 13 2-25 Table 2-26 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions DC I/O Standard Commercial1 Industrial2 IIL IIH IIL3 IIH4 µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCMOS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 1.5 V LVCMOS 10 10 15 15 1.2 V LVCMOS5 10 10 15 15 1.2 V LVCMOS Wide Range5 10 10 15 15 3.3 V PCI 10 10 15 15 3.3 V PCI-X 10 10 15 15 3.3 V GTL 10 10 15 15 2.5 V GTL 10 10 15 15 3.3 V GTL+ 10 10 15 15 2.5 V GTL+ 10 10 15 15 HSTL (I) 10 10 15 15 HSTL (II) 10 10 15 15 SSTL2 (I) 10 10 15 15 SSTL2 (II) 10 10 15 15 SSTL3 (I) 10 10 15 15 SSTL3 (II) 10 10 15 15 Notes: 1. Commercial range (0°C < TA < 70°C) 2. Industrial range (–40°C < TA < 85°C) 3. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3V < VIN <VIL. 4. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 5. Applicable to devices operating at VCCI VCC. |
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