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AS8202NF Scheda tecnica(PDF) 8 Page - ams AG

Il numero della parte AS8202NF
Spiegazioni elettronici  TTP-C2NF Communication Controller
PDF  25 Pages
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Produttore elettronici  AMSCO [ams AG]
Homepage  http://www.ams.com
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AS8202NF Scheda tecnica(HTML) 8 Page - ams AG

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TTP-C2NF Communication Controller – Data Sheet
AS8202NF
Rev. 1.7, Copyright 2000-2007, austriamicrosystems AG and TTChip Entwicklungsgesellschaft mbH. All rights reserved.
7
Pin
Name
Dir
Function
8
RXER0
IPU
TTP Bus Channel 0: Receive Error (MII mode)
9
RXCLK0
IPD
TTP Bus Channel 0: Receive Clock (MII mode)
10
RXDV0
IPU
TTP Bus Channel 0: Receive Data Valid (MII mode)
14
TXD1
OPU
TTP Bus Channel 1: Transmit Data
15
CTS1
OPD
TTP Bus Channel 1: Transmit Enable
20
RXD1
IPU
TTP Bus Channel 1: Receive Data
16
TXCLK1
IPD
TTP Bus Channel 1: Transmit Clock (MII mode)
17
RXER1
IPU
TTP Bus Channel 1: Receive Error (MII mode)
18
RXCLK1
IPD
TTP Bus Channel 1: Receive Clock (MII mode)
19
RXDV1
IPU
TTP Bus Channel 1: Receive Data Valid (MII mode)
35-39, 42-48
A[11:0]
I
Host Interface (CNI) Address Bus1
51-58, 62-69
D[15:0]
I/O
Host Interface (CNI) Data Bus, tristate
76
CEB
IPU
Host Interface (CNI) Chip Enable, active low
77
OEB
IPU
Host interface (CNI) output enable, active low
78
WEB
IPU
Host interface (CNI) write enable, active low
79
READYB
OPU
Host interface (CNI) transfer finish signal, active low, open drain2
28
INTB
OPU
Host interface (CNI) time signal (interrupt), active low, open drain
31-33
LED[2:0]
OPD
Configurable generic output port
1, 27, 40
nc
Not connected, leave open
Note 1: The device is addressed at 16-bit data word boundaries. If the device is connected to a CPU with a byte-granular address bus, remember that
A[11:0] of the AS8202NF device has to be connected to A[12:1] of the CPU (considering a little endian CPU address bus).
Note 2: At de-assertion READYB is driven to the inactive value (high) for a configurable time.
5.1. Pin Directions
Dir
Function
I
TTL Input
IPU
TTL Input with Internal Weak Pull-Up
IPD
TTL Input with Internal Weak Pull-Down
I/O
TTL Input/Output with Tristate
OPU
TTL Output with Internal Weak Pull-Up at Tristate
OPD
TTL Output with Internal Weak Pull-Down at Tristate
A
Analog CMOS Pin
P
Power Pin
6 . E l e c t r i c a l Sp e c i f i c a t i o n s
6.1. Absolute Maximum Ratings (Non Operating)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC Supply Voltage
VDD
-0.3
5.0
V
Input Voltage
Vin
any pin
-0.3
VDD+0.3
V
Input Current
Iin
any pin, TA=25°C
-100
100
mA
Storage Temperature
Tstrg
-55
150
°C
Soldering Temperature
Tsold
t=10 sec, Reflow and Wave
235
°C
Humidity
H
5
85
%
Electrostatic Discharge
ESD
HBM: 1KV Mil.std.883, Method 3015.7
1000
V
Note:
Stresses higher than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device under these or any other conditions higher than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability (e.g. hot carrier
degradation).
6.2. Recommended Operating Conditions
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC Supply Voltage1
VDD
VSS=0V
3.0
3.3
3.6
V



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