DAC5687IPZP datasheet(31/79 Pages) TI

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Address: 0x1D, 0x1E, and 0x1F – Reserved

DAC5687

SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006

BIT 7

BIT 0

Factory use only

Reserved for factory use only.

BIT 7

BIT 0

atest(4:0)

phstr_del(1:0)

unused

atest(4:0): Can be used to enable clock output at the PLLLOCK pin according to Table 5. Pin EXTLO must be

open when atest(4:0) is not equal to 00000.

Table 5. PLLLOCK Output

atest(4:0)

PLLLOCK Output Signal

PLL Enabled (PLLVDD = 3.3 V)

PLL Disabled (PLLVDD = 0 V)

11101

fDAC

Normal operation

11110

fDAC divided by 2

Normal operation

11111

fDAC divided by 4

Normal operation

All others

Normal operation

phstr_del: Adjusts the initial phase of the fS/2 and fS/4 blocks cmix block after PHSTR.

BIT 7

BIT 0

Factory use only

phstr_clkdiv_sel

phstr_clkdiv_sel: Selects the clock used to latch the PHSTR input when restarting the internal dividers. When

set, the full DAC sample rate CLK2 signal latches PHSTR, and when cleared, the divided down input clock

signal latches PHSTR.

Writes have no effect and reads are 0x00.

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