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DP83620 Scheda tecnica(PDF) 21 Page - Texas Instruments |
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DP83620 Scheda tecnica(HTML) 21 Page - Texas Instruments |
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21 / 105 page ![]() TX_CLK TX_EN 0 0 1 1 T2.14.1 T2.14.2 PMD Output Pair PMD Output Pair T2.13.1 TX_CLK TX_EN TXD[3:0] PMD Output Pair DP83620 www.ti.com SNLS339C – JANUARY 2011 – REVISED APRIL 2013 4.17 AC Specifications — 10BASE-T MII Transmit Timing (Start of Packet) Parameter Description Notes Min Typ Max Units T2.13.1 Transmit Output Delay from the Falling 10 Mb/s MII mode 3.5 bits Edge of TX_CLK(1) (1) 1 bit time = 100 ns in 10 Mb/s. 4.18 AC Specifications — 10BASE-T MII Transmit Timing (End of Packet) Parameter Description Notes Min Typ Max Units T2.14.1 End of Packet High Time (with '0' 250 300 ns ending bit) T2.14.2 End of Packet High Time (with '1' 250 300 ns ending bit) Copyright © 2011–2013, Texas Instruments Incorporated Electrical Specifications 21 Submit Documentation Feedback Product Folder Links: DP83620 |
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