AT49F080/080T

2

To allow for simple in-system reprogrammability, the

AT49F080 does not require high input voltages for pro-

gramming. 5-volt-only commands determine the read and

programming operation of the device. Reading data out of

the device is similar to reading from an EPROM. Repro-

gramming the AT49F080 is performed by erasing the entire

8 megabits of memory and then programming on a byte-by-

byte basis. The typical byte programming time is a fast 10

µs. The end of a program cycle can be optionally detected

by the DATA polling feature. Once the end of a byte pro-

gram cycle has been detected, a new access for a read or

program can begin. The typical number of program and

erase cycles is in excess of 10,000 cycles

The optional 16K bytes boot block section includes a repro-

gramming write lock out feature to provide data integrity.

The boot sector is designed to contain user secure code,

and when the feature is enabled, the boot sector is perma-

nently protected from being reprogrammed.

Block Diagram

Device Operation

READ: The AT49F080 is accessed like an EPROM.

When CE and OE are low and WE is high, the data stored

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state whenever CE or OE is high. This dual-

line control gives designers flexibility in preventing bus con-

tention.

ERASURE: Before a byte can be reprogrammed, the

1024K bytes memory array (or 1008K bytes if the boot

block featured is used) must be erased. The erased state

of the memory bits is a logical “1”. The entire device can be

erased at one time by using a 6-byte software code. The

software chip erase code consists of 6-byte load com-

mands to specific address locations with a specific data

pattern (please refer to the Chip Erase Cycle Waveforms).

After the software chip erase has been initiated, the device

will internally time the erase operation so that no external

clocks are required. The maximum time needed to erase

been enabled, the data in the boot sector will not be

erased.

BYTE PROGRAMMING: Once the memory array is

erased, the device is programmed (to a logical “0”) on a

byte-by-byte basis. Please note that a data “0” cannot be

programmed back to a “1”; only erase operations can con-

vert “0”s to “1”s. Programming is accomplished via the

internal device command register and is a 4 bus cycle oper-

ation (please refer to the Command Definitions table). The

device will automatically generate the required internal pro-

gram pulses.

The program cycle has addresses latched on the falling

edge of WE or CE, whichever occurs last, and the data

latched on the rising edge of WE or CE, whichever occurs

cycle time. The DATA polling feature may also be used to

indicate the end of a program cycle.

BOOT BLOCK PROGRAMMING LOCKOUT: The device

has one designated block that has a programming lockout

feature. This feature prevents programming of data in the

designated block once the feature has been enabled. The

size of the block is 16K bytes. This block, referred to as the

boot block, can contain secure code that is used to bring up

the system. Enabling the lockout feature will allow the boot

code to stay in the device while data in the rest of the

device is updated. This feature does not have to be acti-

vated; the boot block's usage as a write protected region is

OE, CE, AND WE

LOGIC

Y DECODER

X DECODER

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(1008K BYTES)

OE

WE

CE

ADDRESS

INPUTS

GND

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

03FFFH

00000H

INPUT/OUTPUT

BUFFERS

DATA LATCH

Y-GATING

OPTIONAL BOOT

BLOCK (16K BYTES)

MAIN MEMORY

(1008K BYTES)

FC000H

00000H

AT49F080T

AT49F080

DATA INPUTS/OUTPUTS

I/O7 - I/O0

8

FFFFFH

FFFFFH