LTC1290BCSW datasheet(21/32 Pages) LINER

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LTC1290

1290fe

APPLICATI

I FOR ATIO

maximum clock rates (ACLK = 4MHz and SCLK = 2MHz).

Figures 11 and 12 show examples of adequate and poor

op amp settling.

HORIZONTAL: 500ns/DIV

Figure 11. Adequate Settling of Op Amps Driving Analog Input

HORIZONTAL: 20

µs/DIV

Figure 12. Poor Op Amp Settling Can Cause A/D Errors

RC Input Filtering

It is possible to filter the inputs with an RC network as shown

in Figure 13. For large values of CF (e.g., 1µF), the capacitive

input switching currents are averaged into a net DC current.

Therefore, a filter should be chosen with a small resistor and

large capacitor to prevent DC drops across the resistor. The

magnitude of the DC current is approximately IDC =

(100pF)(VIN/tCYC) and is roughly proportional to VIN. When

running at the minimum cycle time of 20

µs, the input

current equals 25

µA at VIN = 5V. In this case, a filter resistor

of 5

Ω will cause 0.1LSB of full-scale error. If a larger filter

resistor must be used, errors can be eliminated by increas-

ing the cycle time as shown in the typical curve of Maximum

Filter Resistor vs Cycle Time.

Figure 13. RC Input Filtering

RFILTER

VIN

CFILTER

LTC1290 F13

LTC1290

"+"

"–"

IDC

Input Leakage Current

Input leakage currents can also create errors if the source

resistance gets too large. For instance, the maximum input

leakage specification of 1

µA (at 125°C) flowing through a

source resistance of 1k

Ω will cause a voltage drop of 1mV

or 0.8LSB. This error will be much reduced at lower

temperatures because leakage drops rapidly (see the

typical curve of Input Channel Leakage Current vs Tem-

perature).

Noise Coupling Into Inputs

High source resistance input signals (>500

Ω) are more

sensitive to coupling from external sources. It is prefer-

able to use channels near the center of the package (i.e.,

CH2 to CH7) for signals which have the highest output

resistance because they are essentially shielded by the

pins on the package ends (DGND and CH0). Grounding

any unused inputs (especially the end pin, CH0) will also

reduce outside coupling into high source resistances.

4. Sample-and-Hold

Single-Ended Inputs

The LTC1290 provides a built-in sample-and-hold (S&H)

function for all signals acquired in the single-ended mode

(COM pin grounded). This sample-and-hold allows the

LTC1290 to convert rapidly varying signals (see the typical

curve of S&H Acquisition Time vs Source Resistance). The

input voltage is sampled during the tSMPL time as shown in

Figure 10. The sampling interval begins after the fourth MUX

address bit is shifted in and continues during the remainder

of the data transfer. On the falling edge of the final SCLK, the

S&H goes into hold mode and the conversion begins. The

voltage will be held on either the 8th, 12th or 16th falling edge

of the SCLK depending on the word length selected.

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