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T89C51RD2-3CWC-L Scheda tecnica(PDF) 81 Page - ATMEL Corporation |
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T89C51RD2-3CWC-L Scheda tecnica(HTML) 81 Page - ATMEL Corporation |
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81 / 86 page ![]() 81 Rev. F - 15 February, 2001 T89C51RD2 9.5.6. External Data Memory Read Cycle 9.5.7. Serial Port Timing - Shift Register Mode Table 44. Symbol Description Symbol Parameter TXLXL Serial port clock cycle time TQVHX Output data set-up to clock rising edge TXHQX Output data hold after clock rising edge TXHDX Input data hold after clock rising edge TXHDV Clock rising edge to input data valid Table 45. AC Parameters for a Fix Clock Symbol -M -L Units Min Max Min Max TXLXL 300 300 ns TQVHX 200 200 ns TXHQX 30 30 ns TXHDX 0 0 ns TXHDV 117 117 ns ALE PSEN RD PORT 0 PORT 2 A0-A7 DATA IN ADDRESS OR SFR-P2 TAVWL TLLWL TRLAZ ADDRESS A8-A15 OR SFR P2 TRHDZ TWHLH TRLRH TLLDV TRHDX TLLAX TAVDV |
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