MX25L1673E datasheet(21/65 Pages) MCNIX

Il numero della parte	MX25L1673E

Spiegazioni elettronici	16M-BIT [x 1/x 2/x 4] CMOS MXSMIO짰 (SERIAL MULTI I/O) FLASH MEMORY

PDF	65 Pages

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Produttore elettronici	MCNIX [Macronix International]

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21 / 65 page

MX25L1673E

P/N: PM1912

REV. 1.2, JAN. 14, 2014

The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.

The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write

in Progress (WIP) bit still can be checked out during the Write Status Register cycle is in progress. The WIP sets 1

during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL)

bit is reset.

Note: As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

"Table 2. Protected Area Sizes".

Mode

Status register condition

SRWD bit status

Memory

Software protection

mode (SPM)

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

bits can be changed

SRWD bit=0

The protected area cannot

be programmed or erased.

Table 6. Protection Modes

Software Protected Mode (SPM):

When SRWD bit=0, the WREN instruction may set the WEL bit and can change the values of SRWD, BP3,

BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM).

MX25L1673E Scheda tecnica(PDF) 21 Page - Macronix International