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CS42L50 Scheda tecnica(PDF) 42 Page - Cirrus Logic |
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CS42L50 Scheda tecnica(HTML) 42 Page - Cirrus Logic |
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42 / 48 page ![]() CS42L50 42 DS544PP1 LR C K SC L K Le ft C h an n e l R ig h t C han ne l SD A T A 654 3210 987 15 14 13 12 11 10 10 654 32 10 987 15 14 13 12 11 10 17 16 17 16 32 clocks Figure 28. Right Justified, 18-bit data Right Justified, 18-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 36 Cycles per LRCK Period. LR C K SC LK Le ft C hann el R ight C h anne l SD A T A 6 5432 10 98 7 15 14 13 12 11 10 10 65 432 10 98 7 15 14 13 12 11 10 17 16 17 16 32 clocks 19 18 19 18 Right Justified, 20-Bit Data. Data Valid on Rising Edge of SCLK. SCLK Must Have at Least 40 Cycles per LRCK Period. Figure 29. Right Justified, 20-bit data LR C K SC L K Le ft C h an n e l R ight C h a nne l SD A T A +3 +2 +1 LSB +5 +4 MSB -1 -2 -3 -4 -5 +3 +2 +1 LSB +5 +4 MSB -1 -2 -3 -4 I2S, up to 24-Bit Data. Data Valid on Rising Edge of SCLK Figure 30. I2S, up to 24-bit data |
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