CS43L42 datasheet(35/40 Pages) CIRRUS

35 / 40 page

CS43L42

DS481PP2

Figure 22. CS43L42 Control Port Mode - Serial Audio Format 3

LRCK

SCLK

L e ft C h a n n e l

SDATA

4321

23 22 21 20 19 18

432

23 22 21 20 19 18

3 2 c lo cks

R igh t C h a n ne l

Internal SCLK Mode

External SCLK Mode

Right Justified, 24-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Right Justified, 24-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 48 Cycles per LRCK Period

Figure 23. CS43L42 Control Port Mode - Serial Audio Format 4

L RCK

SCL K

Le ft C h an n e l

R ig h t C h ann el

SD A T A

654

3210

987

15 14 13 12 11 10

6543

210

987

15 14 13 12 11 10

17 16

32 clocks

19 18

Internal SCLK Mode

External SCLK Mode

Right Justified, 20-Bit Data

INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Right Justified, 20-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 40 Cycles per LRCK Period

Figure 24. CS43L42 Control Port Mode - Serial Audio Format 5

LRCK

SCLK

L e ft C h a n n e l

R igh t C h a n ne l

SDATA

4321

987

15 14 13 12 11 10

432

15 14 13 12 11 10

32 c lo cks

Internal SCLK Mode

External SCLK Mode

Right Justified, 16-Bit Data

INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128

INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192

Right Justified, 16-Bit Data

Data Valid on Rising Edge of SCLK

SCLK Must Have at Least 32 Cycles per LRCK Period

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