CS4630 datasheet(31/38 Pages) CIRRUS

31 / 38 page

CS4630

DS445PP1

GNT# - Master Grant, Input, Active Low

GNT# is driven by the system arbiter to indicate to the device that the PCI bus has been

granted.

PERR# - Parity Error, I/O, Active Low

PERR# is used for reporting data parity errors on the PCI bus.

SERR# - System Error, Open Drain Output, Active Low

SERR# is used for reporting address parity errors and other catastrophic system errors.

INTA# - Host Interrupt A (for SP), Open Drain Output, Active Low

INTA# is the level triggered interrupt pin dedicated to servicing internal device interrupt

sources.

PCICLK - PCI Bus Clock, Input

PCICLK is the PCI bus clock for timing all PCI transactions. All PCI synchronous signals are

generated and sampled relative to the rising edge of this clock.

RST# - PCI Device Reset, Active Low

RST# is the PCI bus master reset.

VDD5REF: Clean 5 V (or 3.3 V) Power Supply

VDD5REF is the power connection pin for the 5 V PCI pseudo supply for the PCI bus drivers.

This pin enables the PCI interface to support and be tolerant of 5 Volt signals. It must be

connected to +5 Volts. If the System PCI Bus is known to support only +3.3 V signal levels,

then this pin can be connected to +3.3 V or +3.3 V_Aux when supporting PME generation

from D3cold.

PCIVDD[8:0] - PCI Bus Driver Power Supply

PCIVDD pins are the PCI driver power supply pins. These pins must have a nominal

+3.3 Volts.

PCIGND[8:0] - PCI Bus Driver Ground Pins

PCIGND pins are the PCI driver ground reference pins.

12.2 PCI Power Management Interface Pins

PME# - PCI Power Management Event, Open Drain Output, Active Low

PME# signals a power management event. This signal can go low because of an AC ‘97 2.0

Codec or SP software.

CS4630 Scheda tecnica(PDF) 31 Page - Cirrus Logic