CS5180

18

MODE — Modulator Mode

MODE is held at a logic high for normal operation. In normal operation the device utilizes the

digital decimation filter and calibration circuitry. MODE = 0 puts the part in modulator-only

mode whereby most of the digital circuitry is powered-down and the modulator bit-stream is

output from the SDO and SDO pins.

SYNC — Synchronization of Filter

The SYNC input can be used to restart the digital filter of the converter at the beginning of its

convolution cycle. The SYNC input is used to synchronize the filters of multiple converters in

a system. When the SYNC pin goes high, the filter will be initialized and will begin its

convolution cycle on the next rising edge of MCLK. If not used, tie sync to DGND.

MFLAG — Invalid Conversion Flag

MFLAG goes high if the modulator portion of the converter goes unstable. If MFLAG is high,

the output data from the converter may be invalid.

MCLK, MCLK — Master Clock Signal

Master clock input accepts a CMOS level clock input to the converter with worst case duty

cycle of 45-55% (typically 25.6 MHz). MCLK is not actually used inside the device, but can

be used for radiated noise cancellation if MCLK and MCLK are run adjacent to each other on

the PC board.