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CS5331A Scheda tecnica(PDF) 9 Page - Cirrus Logic

Il numero della parte CS5331A
Spiegazioni elettronici  8-Pin, Stereo A/D Converter for Digital Audio
PDF  30 Pages
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS5331A Scheda tecnica(HTML) 9 Page - Cirrus Logic

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LRCK is automatically detected during power-up
and internal dividers are set to generate the ap-
propriate internal clocks.
CS5330A
The CS5330A data output format is shown in
Figure 2. Notice that the MSB is clocked by the
transition of LRCK and the remaining seventeen
data bits are clocked by the falling edge of
SCLK. The data bits are valid during the rising
edge of SCLK.
CS5331A
The CS5331A data output format is shown in
Figure 3. Notice the one SCLK period delay be-
tween the LRCK transitions and the MSB of the
data. The falling edges of SCLK cause the ADC
to output the eighteen data bits. The data bits are
valid during the rising edge of SCLK. LRCK is
also inverted compared to the CS5330A inter-
face. The CS5331A interface is compatible with
I
2S.
0
1
2
18
19
20 21
22
31
0
1
2
18
19
20 21
22
23
31
0
1
SCLK
LRCK
Left Audio Data
Right Audio Data
17
16
10
17
16
1
0
SDATA
3
3
30
Figure 3. Data Output Timing - CS5331A (I
2S compatible)
0
1
2
18
19
20 21
22
31
0
1
2
18
19
20 21
22
23
31
0
1
SCLK
LRCK
Left Audio Data
Right Audio Data
17
16
10
17
16
1
0
SDATA
17
17
30
Figure 2. Data Output Timing - CS5330A
CS5330A/CS5331A
DS138F2
9



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