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CY7C0430V
PRELIMINARY
21
Table 1. Read/Write and Enable Operation (Any Port)[40, 41, 42]
Inputs
Outputs
OE
CLK
CE0
CE1
R/W
I/O0–I/O17
Operation
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DIN
Write
L
L
H
H
DOUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
Table 2. Address Counter and Counter-Mask Register Control Operation (Any Port)[40, 43, 44]
CLK MRST CNTRST MKLD CNTLD CNTINC CNTRD MKRD
Mode
Operation
X
L
X
X
X
X
X
X
Master-
Reset
Counter/Address Register Reset and Mask
Register Set (resets entire chip as per reset
state table)
H
L
X
X
X
X
X
Reset
Counter/Address Register Reset
H
H
L
X
X
X
X
Load
Load of Address Lines into Mask Register
H
H
H
L
X
X
X
Load
Load of Address Lines into Counter/Address
Register
H
H
H
H
L
X
X
Incre-
ment
Counter Increment
H
H
H
H
H
L
X
Read-
back
Readback Counter on Address Lines
H
H
H
H
H
H
L
Read-
back
Readback Mask Register on Address Lines
H
H
H
H
H
H
H
Hold
Counter Hold
Notes:
40. “X” = “don’t care,” “H” = VIH, “L” = VIL.
41. OE is an asynchronous input signal.
42. When CE changes state, deselection and read happen after one cycle of latency.
43. CE0 = OE = VIL; CE1 = R/W = VIH.
44. Counter operation and mask register operation is independent of Chip Enables.
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