W199
PRELIMINARY
12
SDRAM 0:11,_F Clock Outputs (Lump Capacitance Test Load = 22 pF)
Parameter
Description
Test Condition/Comments
SDRAMIN =
66.8 MHz
SDRAMIN =
100 MHz
SDRAMIN =
133 MHz
Unit
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
tP
Period
Measured on rising edge at
1.5V
15
15.5
10
10.5
7.5
8.0
ns
tH
High Time
Duration of clock cycle above
2.4V
5.2
3.0
1.87
ns
tL
Low Time
Duration of clock cycle below
0.4V
5.0
2.0
1.67
ns
tR
Output Rise Edge
Rate
Measured from 0.4V to 2.4V
1
4
1
4
1
4
V/ns
tF
Output Fall Edge
Rate
Measured from 2.4V to 0.4V
1
4
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling
edge at 1.5V
45
55
45
55
45
55
%
tJC
Jitter,
Cycle-to-Cycle
Measured on rising edge at
1.5V. Maximum difference of
cycle time between two adja-
cent cycles.
250
250
250
ps
tSK
Output Skew
Measured on rising and falling
edge at 1.5V
250
250
250
ps
tPD
Propagation
Delay
Measured from SDRAMIN
3.7
3.7
3.7
ns
Zo
AC output
Impedance
Average value during switching
transition. Used for determin-
ing series termination value.
15
15
15
Ω
REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V.
45
55
%
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms from
power-up. Short cycles exist prior to frequency stabili-
zation.
3ms
Zo
AC Output Impedance
Average value during switching transition. Used for de-
termining series termination value.
40
Ω
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