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ADS5542

Serial Programming Register

Control Logic

Timing Circuitry

Internal

Reference

Output

Control

CLKOUT

CLK+

CLK−

CM

OVR

DFS

Digital

Error

Correction

14-Bit

Pipeline

ADC

Core

S&H

SCLK

SDATA

SEN

D0

D13

ABSOLUTE MAXIMUM RATINGS

ADS5542

SBAS308D – MAY 2004 – REVISED FEBRUARY 2007

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be

more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

DESIGNATOR

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

ADS5542IPAP

Tray, 160

ADS5542

PAP

–40

°C to 85°C

ADS5542I

PowerPAD

ADS5542IPAPR

Tape and Reel, 1000

(1)

For the most current product and ordering information, see the Package Option Addendum at the end of this data sheet.

(2)

Thermal pad size: 3,5 mm

× 3,5 mm (min), 4 mm x 4 mm (max). θ

trace and pad soldered directly to a JEDEC standard, four-layer, 3 in

× 3 in PCB.

ADS5500

UNIT

–0.3 to 3.7

V

Supply Voltage

±0.1

V

V

V

V

Operating temperature range

–40 to 85

°C

Junction temperature

105

°C

Storage temperature range

–65 to 150

°C

(1)

Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not implied.

(2)

If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25

Ω should be added in series with each of the analog

input pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycle

of the overshoot should be limited to less than 5% for inputs up to 3.9 V.

(3)

The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as a

percentage. The total time of overshoot is the integrated time of all overshoot occurences over the lifetime of the device.

2

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