PBL3776-1 datasheet(6/8 Pages) ERICSSON

6 / 8 page

PBL 3776/1

For accurate current regulation, the

sensing resistor should be a 0.5 - 1.5 W

precision resistor, i. e. less than 1%

tolerance and low temperature

coefficient.

Recirculating diodes

Care must be taken to assure that the

recirculating current from the motor

winding has a free path at all times,

when designing the external H-bridge

otherwise may the voltage reach

dangerous levels at the outputs. See

figure 6. Make sure that there are

recirculating diodes included in the

transistors, or if not design in external

diodes. Also make sure that these

diodes are sufficient for the application

i.e. regarding recovery time, voltage

drop etc.

Current sense filtering

At turn-on a current transient occurs,

due to the recovery of the recirculation

diodes and the capacitance of the motor

winding. To prevent this transient from

reseting the flip-flops through the

current sensing comparators, the clock

oscillator generates a blanking pulse at

turn-on. The blanking pulse disables the

comparators for a short time. Thereby

preventing any voltage transient across

the sensing resistor from reseting the

flip-flop during the time blanking.

Select the blanking pulse time to be

longer than the duration of the switching

transients by selecting a proper C

value. The time is calculated as:

b = 210 • CT

[s]

As the C

T value may vary from approxi-

mately 2 200 pF to 33 000 pF, a

blanking time ranging from 0.5

µs to 7 µs

is possible. Nominal value is 4 700 pF,

which gives a blanking time of 1.0

µs.

As the filtering action introduces a

small delay, the peak value across the

sensing resistor, and hence the peak

motor current, will reach a slightly

higher level than what is defined by the

reference voltage. The filtering delay

also limits the minimum possible output

current. As the output will be on for a

short time each cycle, equal to the digital

filtering blanking time plus additional

internal delays, a small amount of

current will flow through the winding.

Typically this current is 1-10 % of the

maximum output current set by R

When optimizing low current perfor-

mance, the filtering may be done by

adding an external low pass filter in

series with the comparator C input, see

figure 5. In this case the digital blanking

time should be as short as possible. The

recommended filter component values

are 1 kohm and 1000 pF. The transient

may be reduced by adding external

recircula-ting diodes. These diodes

should be of the fast switching type. By

doing this the filter delay will be

minimized. Lowering the switching

frequency also helps reduce the

minimum output current.

It is recommended to add the resistor

R8 in the feedback loop in order to

prevent the switching transient from

damaging the C inputs. See figure 5.

To create an absolute zero current,

the Dis input should be HIGH.

Switching frequency

The frequency of the clock oscillator is set

by the timing components R

T and CT at

the RC-pin. Since C

T sets the digital filter

blanking time, the clock oscillator

frequency is adjusted by R

T. The value of

T is limited to 2 - 20 kohm. The frequen-

cy is approximately calculated as:

s = 1 / ( 0.77 • RT • CT)

Nominal component values of 12 kohm

and 4 700 pF results in a clock

frequency of 23.0 kHz. A lower

frequency will result in higher current

ripple, but may improve low level

linearity. A higher clock frequency

reduces current ripple, but increases the

switching losses in the IC and possibly

the iron losses in the motor.

Phase inputs

A logic HIGH on a Phase input causes

the TxBL pin to sink current, low voltage,

and the TxAU pin to source current, high

voltage. A logic LOW causes the TxAL

to sink current, low voltage, and the

TxBU to source current, high voltage. A

time delay prevents cross conduction in

the H-bridge when changing the Phase

input.

See truth table fig. 7.

Dis (Disable) inputs

A logic HIGH on the Dis inputs will turn off

all four transistors of the outputs, which

results in a rapidly decreasing output

current to zero. See truth table fig 7.

R (Reference) inputs

The Vref inputs of the PBL 3776/1 have

a voltage divider with a ratio of 1 to 10 to

reduce the external reference voltage to

an adequate level. The divider consists

of closely matched resistors . Nominal

input reference voltage is 5 V.

Interference

Due to the switching operation of

PBL 3776/1, noise and transients are

generated and coupled into adjacent

circuitry. To reduce potential interference

there are a few basic rules to follow:

• Use separate ground leads for power

ground (the ground connection of R

S),

the ground leads of PBL 3776/1, and

the

ground of external analog and

digital

circuitry. The grounds should be

Figure 6. Output stage with current paths

during turn-on, turn-off and phase shift.

Figure 7. Truth table.

Vmm

Fast Current Decay

Slow Current Decay

Motor Current

Time

TxBU = 1

TxBL = x

TxAU = x

TxAU = 0

TxBU = x

TxBL = 0

TxAU = 1

TxAU = x

All four off

Disable

Phase

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