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M2S005 Scheda tecnica(PDF) 5 Page - Microsemi Corporation

Il numero della parte M2S005
Spiegazioni elettronici  FPGA and SoC Product Catalog
PDF  27 Pages
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Produttore elettronici  MICROSEMI [Microsemi Corporation]
Homepage  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

M2S005 Scheda tecnica(HTML) 5 Page - Microsemi Corporation

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www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga
• Highest number of 5G
transceivers1
• Highest number of GPIO1
• Highest number of PCI
compliant 3.3 V I/O1
• Only FPGA with hardened
memory subsystem
• Only non-volatile and instant-on
mainstream FPGA
• 10x lower static power with
the same performance
• 1 mW in Flash*Freeze mode
• Only FPGA with SEU immune
fabric and mainstream features
• Extended temperature support
(up to 125ºC Tj)
• Built-in state-of-the-art design
security for all devices
• Root-of-trust
• Easy-to-use
IGLOO2
The FPGA with high level of integration at the lowest total system cost
The IGLOO2 FPGA family provides a 4-input look-up table (LUT) based fabric, 5G transceivers, high-speed general purpose I/O (GPIO), block RAM and
digital signal processing (DSP) blocks in a differentiated, cost- and power-optimized architecture. This next-generation IGLOO2 FPGA architecture offers up to
5x more logic density and 3x more fabric performance than its predecessors and combines a non-volatile flash-based fabric with the highest number of GPIO,
5G serialization/deserialization (SERDES) interfaces and PCI Express® (PCIe®) endpoints when compared to other products in its class.
IGLOO2 Devices
 
Features
M2GL005
M2GL010
M2GL025
M2GL050
M2GL090
M2GL100
M2GL150
Logic/DSP
Maximum Logic Elements
(4LUT + DFF)1
6,060
12,084
27,696
56,340
86,316
99,512
146,124
Math Blocks (18x18)
11
22
34
72
84
160
240
PLLs and CCCs
2
6
8
SPI/HPDMA/PDMA
1 each
Fabric Interface Controllers (FICs)
1
2
Security
AES256, SHA256, RNG
AES256, SHA256, RNG, ECC, PUF
Memory
eNVM (K Bytes)
128
256
512
LSRAM 18 K Blocks
10
21
31
69
109
160
236
uSRAM 1 K Blocks
11
22
34
72
112
160
240
eSRAM (K Bytes)
64
Total RAM (K bits)
703
912
1104
1826
2586
3552
5000
High Speed
DDR Controllers
1x18
2x36
1x18
2x36
SERDES Lanes (T)
0
4
8
4
8
16
PCIe End Points
0
1
2
4
User I/Os
MSIO (3.3 V)
115
123
157
139
309
292
292
MSIOD (2.5 V)
28
40
40
62
40
106
106
DDRIO (2.5 V)
66
70
70
176
76
176
176
Total User I/O
209
233
267
377
425
574
574
Note:
1. Total logic may vary based on utilization of DSP and memories in your design. Please see the IGLOO2 Fabric UG for details.
2. Feature availablility is package dependent.
I/Os per Package
Type
FCS325
VF256
VF400
FCV484
VQ144
FG484
FG676
FG896
FC1152
Pitch (mm)
0.5
0.8
0.8
0.8
0.5
1.0
1.0
1.0
1.0
Length x Width (mm)
11x11
14x14
17x17
19x19
20x20
23x23
27x27
31x31
35x35
Device
I/O
Lanes
I/O
Lanes
I/O
Lanes
I/O
Lanes
I/O
Lanes
I/O
Lanes
I/O
Lanes
I/O
Lanes
I/O
Lanes
M2GL005 (S)
171
83¹
209
M2GL010 (S/T/TS)
148¹
195
4
75¹
233
4
M2GL025 (S/T/TS)
180
2
148¹
207
4
267
4
M2GL050 (S/T/TS)
200
2
207
4
267
4
377
8
M2GL090 (S/T/TS)²
200¹
267
4
425
4
M2GL100 (S/T/TS)
273¹
574
8
M2GL150 (S/T/TS)
273¹
574
16
Note:
1 Preliminary.
2. 090 FCS325 is 11x13.5 package dimension.



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