1- 2

v5.9

The

proprietary

architecture

provides

granularity comparable to gate arrays.

(Figure 1-1). Each tile can be configured as a three-input

logic function (e.g., NAND gate, D-Flip-Flop, etc.) by

programming

the

appropriate

flash

switch

interconnections (Figure 1-2 and Figure 1-3 on page 1-3).

Tiles and larger functions are connected with any of the

four levels of routing hierarchy. Flash switches are

distributed

throughout

the

device

to

provide

nonvolatile, reconfigurable interconnect programming.

Flash switches are programmed to connect signal lines to

the appropriate logic cell inputs and outputs. Dedicated

high-performance lines are connected as needed for fast,

low-skew global signal distribution throughout the core.

Maximum core utilization is possible for virtually any

design.

SRAM blocks with built-in FIFO/RAM control logic.

Programming

options

include

synchronous

or

asynchronous operation, two-port RAM configurations,

user-defined depth and width, and parity generation or

checking.

Refer

to

the

"Embedded

Memory

Specifications"

section

on

page 2-54

for

more

information.

Figure 1-2 • Flash Switch

256x9 Two-Port SRAM

or FIFO Block

Logic Tile

256x9 Two Port SRAM

or FIFO Block

RAM Block

RAM Block

I/Os

Sensing

Switching

Switch In

Switch Out

Word

Floating Gate