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NVT2004TL Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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NVT2004TL Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
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3 / 33 page ![]() NVT2003_04_06 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 5 — 19 February 2014 3 of 33 NXP Semiconductors NVT2003/04/06 Bidirectional voltage-level translator 4. Functional diagram 5. Pinning information 5.1 Pinning 5.1.1 3-bit in TSSOP10 package 5.1.2 4-bit in HXSON12 package Fig 1. Logic diagram of NVT2003/04/06 (positive logic) 002aae132 A1 An VREFA GND VREFB B1 Bn EN SW SW NVT20xx Fig 2. Pin configuration for TSSOP10 NVT2003DP GND EN VREFA VREFB A1 B1 A2 B2 A3 B3 002aae836 1 2 3 4 5 6 8 7 10 9 Fig 3. Pin configuration for HXSON12U 002aae219 NVT2004TL Transparent top view 112 GND EN 211 VREFA VREFB 310 A1 B1 67 A4 B4 49 A2 B2 58 A3 B3 |
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