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ADS1253 Scheda tecnica(PDF) 3 Page - Texas Instruments |
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ADS1253 Scheda tecnica(HTML) 3 Page - Texas Instruments |
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3 / 23 page ![]() ADS1253 SBAS199B 3 www.ti.com ELECTRICAL CHARACTERISTICS (Cont.) All specifications at TMIN to TMAX, VDD = +5V, CLK = 8MHz, and VREF = 4.096V, unless otherwise specified. ADS1253E PARAMETER CONDITIONS MIN TYP MAX UNITS DIGITAL INPUT/OUTPUT Logic Family CMOS Logic Level: VIH +4.0 +VDD + 0.3 V VIL –0.3 +0.8 V VOH IOH = –500µA +4.5 V VOL IOL = 500µA 0.4 V Input (SCLK, CLK, CHSEL0, CHSEL1) Hysteresis 0.6 V Data Format Offset Binary Two’s Complement POWER-SUPPLY REQUIREMENTS Operation +4.75 +5 +5.25 VDC Quiescent Current 1.5 2 mA Operating Power 7.5 10 mW Power-Down Current 0.4 1 µA TEMPERATURE RANGE Operating –40 +85 °C Storage –60 +100 °C CH1+ ADS1253E CH4– CH1– CH4+ CH2+ V REF GND CH2– 1 2 3 4 16 15 14 13 CH3+ CHSEL1 CH3– CHSEL0 +V DD SCLK DOUT/DRDY CLK 5 6 7 8 12 11 10 9 PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN NAME PIN DESCRIPTION 1 CH1+ Analog Input: Positive Input of the Differen- tial Analog Input 2 CH1– Analog Input: Negative Input of the Differ- ential Analog Input 3 CH2+ Analog Input: Positive Input of the Differen- tial Analog Input 4 CH2– Analog Input: Negative Input of the Differ- ential Analog Input 5 CH3+ Analog Input: Positive Input of the Differen- tial Analog Input 6 CH3– Analog Input: Negative Input of the Differ- ential Analog Input 7+VDD Input: Power-Supply Voltage, +5V 8 CLK Digital Input: Device System Clock. The system clock is in the form of a CMOS- compatible clock. This is a Schmitt-Trigger input. 9 DOUT/DRDY Digital Output: Serial Data Output/Data Ready. This output indicates that a new output word is available from the ADS1253 data output register. The serial data is clocked out of the serial data output shift register using SCLK. 10 SCLK Digital Input: Serial Clock. The serial clock is in the form of a CMOS-compatible clock. The serial clock operates independently from the system clock, therefore, it is pos- sible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW. Holding SCLK HIGH will either ini- tiate a modulator reset for synchronizing multiple converters or enter power-down mode. This is a Schmitt-Trigger input. 11 CHSEL1 Digital Input: Used to select analog input channel. This is a Schmitt-Trigger input. 12 CHSEL0 Digital Input: Used to select analog input channel. This is a Schmitt-Trigger input. 13 GND Input: Ground 14 VREF Analog Input: Reference Voltage Input 15 CH4– Analog Input: Negative Input of the Differ- ential Analog Input 16 CH4+ Analog Input: Positive Input of the Differen- tial Analog Input NOTE: (1) Applies to full-differential signals. |
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