DAC8408FPC3 datasheet(11/16 Pages) AD

11 / 16 page

DAC8408

–11–

REV. A

Figure 7. Quad DAC Bipolar Operation (4-Quadrant Multiplication)

Table II. Bipolar (Offset Binary) Code Table

(Refer to Figure 7)

DAC Data Input

Analog Output

MSB

LSB

(DAC A OR DAC B)

1 1 1 1 1 1 1 1

+VREF

127

128









1 0 0 0 0 0 0 1

+VREF

128









1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

–VREF

128









0 0 0 0 0 0 0 1

–VREF

127

128









0 0 0 0 0 0 0 0

–VREF

128









NOTE

1 LSB = (2

–7) (V

REF) =

128

(VREF)

APPLICATION HINTS

General Ground Management: AC or transient voltages be-

tween AGND and DGND can appear as noise at the DAC8408’s

analog output. Note that in Figures 5 and 6, IOUT2A/IOUT2B and

IOUT 2C/IOUT 2D are connected to AGND. Therefore, it is rec-

ommended that AGND and DGND be tied together at the

DAC8408 socket. In systems where AGND and DGND are tied

together on the backplane, two diodes (1N914 or equivalent)

should be connected in inverse parallel between AGND and

DGND.

Write Enable Timing: During the period when both DS and

R/W are held low, the DAC latches are transparent and the ana-

log output responds directly to the digital data input. To pre-

vent unwanted variations of the analog output, the R/W should

not go low until the data bus is fully settled (DATA VALID).

DAC8408FPC3 Scheda tecnica(PDF) 11 Page - Analog Devices

DAC8408FPC3 Scheda tecnica(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Scheda tecnica Scarica

Link URL