HT82K68 datasheet(13/40 Pages) HOLTEK

13 / 40 page

HT82K68E

August 8, 2000

Preliminary

If an RC oscillator is used, an external resistor

between OSC1 and VDD is needed and the re-

sistance must range from 51kW to 1MW. The

system clock, divided by 4, is available on

OSC2, which can be used to synchronize exter-

nal logic. The RC oscillator provides the most

cost effective solution. However, the frequency

of the oscillation may vary with VDD, tempera-

ture and the chip itself due to process varia-

tions. It is, therefore, not suitable for timing

sensitive operations where accurate oscillator

frequency is desired.

If the Crystal oscillator is used, a crystal across

OSC1 and OSC2 is needed to provide the feed-

back and phase shift needed for oscillator, no

other external components are needed. Instead

of a crystal, the resonator can also be connected

between OSC1 and OSC2 to get a frequency ref-

erence, but two external capacitors in OSC1

and OSC2 are required.

The WDT oscillator is a free running on-chip

RC oscillator, and no external components are

required. Even if the system enters the power

down mode, the system clock is stopped, but the

WDT oscillator still works for a period of ap-

proximately 78 ms. The WDT oscillator can be

disabled by mask option to conserve power.

Watchdog Timer - WDT

The WDT clock source is implemented by a ded-

icated RC oscillator (WDT oscillator) or instruc-

tion clock (system clock divided by 4), decided

by mask options. This timer is designed to pre-

vent a software malfunction or sequence jump-

ing to an unknown location with unpredictable

results. The Watchdog Timer can be disabled by

mask option. If the Watchdog Timer is disabled,

all the executions related to the WDT results in

no operation.

Once the internal WDT oscillator (RC oscillator

normally with a period of 78ms) is selected, it is

first divided by 256 (8-stages) to get the nomi-

nal time-out period of approximately 20 ms.

This time-out period may vary with tempera-

ture, VDD and process variations. By invoking

the WDT prescaler, longer time-out periods can

be realized. Writing data to WS2, WS1, WS0

(bit 2,1,0 of the WDTS) can give different

time-out periods. If WS2, WS1, WS0 are all

equal to 1, the division ratio is up to 1:128, and

the maximum time-out period is 2.6 seconds.

If the WDT oscillator is disabled, the WDT clock

may still come from the instruction clock and

operate in the same manner except that in the

HALT state the WDT may stop counting and

lose its protecting purpose. In this situation the

WDT logic can be restarted by external logic.

The high nibble and bit 3 of the WDTS are re-

served for user defined flags, which can be used

to indicate some specified status.

If the device operates in a noisy environment,

using the on-chip RC oscillator (WDT OSC) is

strongly recommended, since the HALT will

stop the system clock.

WS2

WS1

WS0

Division Ratio

000

1:1

001

1:2

010

1:4

011

1:8

1:16

1:32

1:64

1:128

The WDT overflow under normal operation will

initialize ²chip reset² and set the status bit TO. An

overflow in the HALT mode, initializes a ²warm

reset² only when the PC and SP are reset to zero.

To clear the contents of the WDT (including the

WDT prescaler ), three methods are adopted; ex-

ternal reset (a low level to RESET), software in-

struction(s), or a HALT instruction. There are two

types of software instructions; CLR WDT and

CLR WDT1/CLR WDT2. Of these two types of in-

struction, only one can be active depending on the

mask option -²CLR WDT times selection option².

If the ²CLR WDT² is selected (ie. CLR WDT times

equal one), any execution of the CLR WDT in-

struction will clear the WDT. In case ²CLR WDT1²

and ²CLR WDT2² are chosen (ie. CLRWDT times

equal two), these two instructions must be exe-

WDTS register

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