GMS36 datasheet(53/109 Pages) HYNIX

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5-8

(14) TM n

Naming :

Test Memory Bit

Status :

Comparison results to status

Format :

Operand :

Bit address 0

õ n õ 3

Function :

M(X,Y,n)

à 1?

à 1 when M(X,Y,n)=1, ST à 0 when M(X,Y,n)=0

A test is made to find if the selected memory bit is logic. 1

Status is set depending on the result.

(15) BR a

Naming :

Branch on status 1

Status :

Conditional depending on the status

Format :

Operand :

Branch address a (Addr)

Function :

When ST =1 , PA

à PB, PC à a(Addr)

When ST = 0, PC

à PC + 1, ST à 1

Note : PC indicates the next address in a fixed sequence that

is actually pseudo-random count.

For some programs, normal sequential program execution can

be change.

A branch is conditionally implemented depending on the status

of results obtained by executing the previous instruction.

• Branch instruction is always conditional depending on the

status.

a. If the status is reset (logic 0), a branch instruction is not

rightly executed but the next instruction of the sequence is

executed.

b. If the status is set (logic 1), a branch instruction is executed

as follows.

• Branch is available in two types - short and long. The former

is for addressing in the current page and the latter for

addressing in the other page. Which type of branch to exeute

is decided according to the PB register. To execute a long

branch, data of the PB register should in advance be modified

to a desired page address through the LPBI instruction.

Chapter 5. INSTRUCTION

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