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ICS8523 Scheda tecnica(PDF) 1 Page - Integrated Circuit Systems |
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ICS8523 Scheda tecnica(HTML) 1 Page - Integrated Circuit Systems |
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1 / 13 page ![]() 8523BG www.icst.com/products/hiperclocks.html REV. B JULY 31, 2001 1 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER BLOCK DIAGRAM PIN ASSIGNMENT ICS8523 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 CLK nCLK PCLK nPCLK Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 0 1 CLK_EN CLK_SEL D Q LE GENERAL DESCRIPTION The ICS8523 is a low skew, high perfor- mance 1-to-4 Differential-to-LVHSTL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS8523 ideal for those applications demanding well defined performance and repeatability. FEATURES • 4 differential 1.8V LVHSTL outputs • Selectable CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL • Maximum output frequency up to 650MHz • Translates any single-ended input signal to 1.8V LVHSTL levels with resistor bias on nCLK input • Output skew: 30ps (maximum) • Part-to-part skew: 150ps (maximum) • Propagation delay: 1.6ns (maximum) • 3.3V core, 1.8V output operating supply • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request HiPerClockS™ ,&6 |
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