IDT72205LB datasheet(10/16 Pages) IDT

Il numero della parte	IDT72205LB

Spiegazioni elettronici	CMOS SyncFIFOO 256 x 18, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18

PDF	16 Pages

Scroll/Zoom	100%

Produttore elettronici	IDT [Integrated Device Technology]

Homepage	http://www.idt.com

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10 / 16 page

IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™

256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18

Commercial And Industrial Temperature Ranges

Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write

Figure 8. Full Flag Timing

WCLK

D0 - D17

RCLK

Q0 - Q17

t DS

tSKEW2

t ENS

t REF

DDD

(first valid write)

t OE

t OLZ

tFRL(1)

tENS

2766 drw 09

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

FF will go HIGH during the current clock cycle. If the

time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then

FF may not change state until the next WCLK edge.

DATA READ

WCLK

D0 - D17

RCLK

Q0 - Q17

t A

t WFF

DATA WRITE

t WFF

t ENH

t ENS

t DS

t WFF

t DS

DATA

WRITE

NEXT DATA READ

t A

NO WRITE

DATA IN OUTPUT REGISTER

LOW

tSKEW1

(1)

t SKEW1

(1)

t ENH

t ENS

2766 drw 10

NOTES:

1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either

2*tCLK + tSKEW2 or tCLK + tSKEW2. The Latency Timing applies only at the Empty Boundary (

EF = LOW).

2. The first word is available the cycle after

EF goes HIGH, always.

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