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IDT7134LA55CB Scheda tecnica(PDF) 6 Page - Integrated Device Technology

Il numero della parte IDT7134LA55CB
Spiegazioni elettronici  HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
PDF  9 Pages
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Produttore elettronici  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7134LA55CB Scheda tecnica(HTML) 6 Page - Integrated Device Technology

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6.04
6
IDT7134SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(1, 3)
2720 drw 09
CE
DATAOUT
VALID DATA (4)
tPD
tAOE(4)
tACE
OE
tHZ(2)
tLZ(1)
tLZ(1)
tPU
50%
50%
ICC
ISB
CURRENT
tHZ(2)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
OE or CE.
3. R/
W = VIH.
4. Start of valid data depends on which timing becomes effective , tAOE, tACE or tAA
5. tAA for RAM Address Access and tSAA for Semaphore Address Access.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(6)
7134X20
(5)
7134X25
7134X35
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
20
—
25
—
35
—
ns
tEW
Chip Enable to End-of-Write
15
—
20
—
30
—
ns
tAW
Address Valid to End-of-Write
15
—
20
—
30
—
ns
tAS
Address Set-up Time
0
—
0
—
0
—
ns
tWP
Write Pulse Width
15
—
20
—
25
—
ns
tWR
Write RecoveryTime
0
—
0
—
0
—
ns
tDW
Data Valid to End-of-Write
15
—
15
—
20
—
ns
tHZ
Output High-Z Time
(1, 2)
—15—
15
—20
ns
tDH
Data Hold Time
(3)
0—
0
—
3—
ns
tWZ
Write Enabled to Output in High-Z
(1, 2)
—15—
15
—20
ns
tOW
Output Active from End-of-Write
(1, 2, 3)
3—
3
—
3—
ns
tWDD
Write Pulse to Data Delay
(4)
—40—
50
—60
ns
tDDD
Write Data Valid to Read Data Delay
(4, 7)
—30—
30
—35
ns
NOTES:
2720 tbl 10
1. Transition is measured
±500mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary
over voltage and temperature, the actual tDH will always be smaller than the actual tOW.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read”.
5. (Commercial only), 0
°C to +70°C temperature range .
6. “X” in part number indicates power rating (SA or LA).
7. tDDD = 35ns for military temperature range.



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