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IA8237-PDW40C Scheda tecnica(PDF) 2 Page - InnovASIC, Inc |
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IA8237-PDW40C Scheda tecnica(HTML) 2 Page - InnovASIC, Inc |
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2 / 4 page ![]() Page 2 of 4 IA8237 Advanced Information Sheet Programmable DMA Controller Copyright © 1999, InnovASIC Inc. Customer Specific IC Solutions The IA8237 is a programmable direct memory access (DMA) mega-function designed to be functionally equivalent to the Intel 8237A and Harris 82C37A devices. The A8237 controls data transfers between memory and peripherals, memory-to-memory transfers, and block memory initialization. Four independently programmable channels are available, and requests may be generated via hardware or software. A block diagram is shown in Figure 1. Functional Block Diagram Figure 1 TIMING AND CONTROL ADSTB MEMR_n MEMW_n IOR_n IOW_n CS_n READY CLK AEN EOP_n RESET PRIORITY ENCODER AND ROTATING PRIORITY LOGIC HDLA HRQ_n DREQ0_n : DREQ3_n DACK0 : DACK3 COMMAND MASK REQUEST DECREMENTOR TEMP WORD COUNT REG INC/DECREMENTOR TEMP ADDRESS REG BASE ADDRESS BASE WORD COUNT READ BUFFER CURRENT ADDRESS CURRENT WORD COUNT READ WRITE BUFFER WRITE BUFFER READ BUFFER IO BUFFER TEMPORARY STATUS MODE READ WRITE COMMAND CONTROL OUTPUT BUFFER IO BUFFER A0 : A3 A4 : A7 DB0 : DB7 16 16 INTERNAL DATA BUS |
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