AD5060 datasheet(13/24 Pages) AD

13 / 24 page

AD5040/AD5060

Rev. A | Page 13 of 24

CH3 2.00V

CH2 50mV

M1.00ms

CH3

1.36V

30mV p-p

4.96V p-p

C3 FALL

∞s

NO VALID

EDGE

C3 RISE

946.2

μs

2.1

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

–10

μs

9.96

μs

–2

μs

–4

μs

–6

μs

–8

μs

VDD = 5.5V

VREF = 4.096V

10% TO 90% RISE TIME = 0.688

μs

SLEW RATE = 1.16V/

μs

DAC

OUTPUT

1.04V

2.04V

Figure 34. Glitch upon Exiting Hardware Power-Down to Zero Scale

Figure 37. Typical Output Slew Rate

0.0010

0.0008

0.0006

0.0004

0.0002

–0.0002

–0.0004

–0.0006

–0.0008

–25

–20

–15

–10

–5

CURRENT (mA)

CODE = MID-SCALE

VDD = 5V, VREF = 4.096V

VDD = 3V, VREF = 2.5V

VDD = 5.5V

VDD = 3V

0.83

0.91

0.90

0.89

0.88

0.87

0.86

0.85

0.84

BIN

Figure 35. Typical Output Load Regulation

Figure 38. IDD Histogram VDD = 3.0 V

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0.02

0.04

0.06

0.08

–25

–20

–15

–10

–5

IOUT (mA)

CODE = MIDSCALE

VDD = 5V, VREF = 4.096V

VDD = 3V, VREF = 2.5V

VDD = 5V, VREF = 4.096V

1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11MORE

BIN

Figure 36. Typical Current Limiting Plot

Figure 39. IDD Histogram VDD = 5.0 V

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