Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

80960CF-33 Scheda tecnica(PDF) 16 Page - Intel Corporation

Il numero della parte 80960CF-33
Spiegazioni elettronici  80960CF-40, -33, -25, -16 32-BIT HIGH-PERFORMANCE SUPERSCALAR EMBEDDED MICROPROCESSOR
PDF  77 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  INTEL [Intel Corporation]
Homepage  http://www.intel.com
Logo INTEL - Intel Corporation

80960CF-33 Scheda tecnica(HTML) 16 Page - Intel Corporation

Back Button 80960CF-33 Datasheet HTML 12Page - Intel Corporation 80960CF-33 Datasheet HTML 13Page - Intel Corporation 80960CF-33 Datasheet HTML 14Page - Intel Corporation 80960CF-33 Datasheet HTML 15Page - Intel Corporation 80960CF-33 Datasheet HTML 16Page - Intel Corporation 80960CF-33 Datasheet HTML 17Page - Intel Corporation 80960CF-33 Datasheet HTML 18Page - Intel Corporation 80960CF-33 Datasheet HTML 19Page - Intel Corporation 80960CF-33 Datasheet HTML 20Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 77 page
background image
10
PRELIMINARY
80960CF-40, -33, -25, -16
A
CLKIN
I
A(E)
H(Z)
R(Z)
CLOCK INPUT is an input for the external clock needed to run the processor. The
external clock is internally divided as prescribed by the CLKMODE pin to produce
PCLK2:1.
CLKMODE
I
A(L)
H(Z)
R(Z)
CLOCK MODE selects the division factor applied to the external clock input (CLKIN).
When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the
processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create
PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in
a system as the clock mode is not latched by the processor. If left unconnected, the
processor internally pulls the CLKMODE pin low, enabling the 2-x clock mode.
PCLK2:1
O
S
H(Q)
R(Q)
PROCESSOR OUTPUT CLOCKS provide a timing reference for all inputs and
outputs. All input and output timings are specified in relation to PCLK2 and PCLK1.
PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexi-
bility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may also
be connected at the processor to form a single clock signal.
VSS
GROUND connections must be connected externally to a VSS board plane.
VCC
POWER connections must be connected externally to a VCC board plane.
VCCPLL
VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.
Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in
noisy environments. Otherwise, VCCPLL should be connected to VCC.
NC
NO CONNECT pins must not be connected in a system.
Table 3. 80960CF Pin Description — Processor Control Signals (Sheet 2 of 2)
Name
Type
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77


Scheda tecnica Scarica

Go To PDF Page


Link URL



Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   Collegamento alla scheda tecnica    |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com