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80960HT Scheda tecnica(PDF) 68 Page - Intel Corporation |
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80960HT Scheda tecnica(HTML) 68 Page - Intel Corporation |
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68 / 102 page ![]() 80960HA/HD/HT 62 Advance Information Datasheet Figure 45. Burst, Pipelined Read Request with Wait States, 8-Bit Bus ADS A31:4, SUP, CT3:0, D/C, LOCK W/R A3:2 BE1/A1, WAIT BLAST DT/R DEN CLKIN D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 D7:0 D' A2 1 D 1 D 1 D 1 A' 21 D D' In- valid Valid In- valid BE0/A0 D31:0, A3:2 = 00, 01, 10, or 11 Valid In- valid A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 = 11 Valid Valid In- valid DP3:0 1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin PCHK 2 Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 Enabled 1 ON 1 X xxxx 8-Bit X x Enabled 1 X xx X xxxxx 1 01 X x 2 00010 Function Bit Value External Ready Control Pipe- Lining Parity Enable NRAD 00 NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. PMCON 1 |
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