8X930AX datasheet(37/38 Pages) INTEL

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ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

RHDZ

Data Float After PSEN# or RD# High

CLK + 10 [max]

1.5 T

CLK - 5 [max]

RHLH

RD# or PSEN# High to ALE High (data)

CLK + 10 [min]

(1.5)T

CLK - 7 [min]

RHLH

PSEN# High to ALE High (inst.)

10 [min]

(0.5)T

CLK - 7 [min]

WHLH

WR# High to ALE High

CLK + 10 [min]

(1.5)T

CLK - 7 [min]

AVDV

Address (mux’ed) Valid to Valid Data/Inst. In

(2+M+N)T

CLK - 60 [max]

(1.5+M+N)T

CLK - 28 [max]

AVRL

Address Valid to RD# or PSEN# Low

(1+M)T

CLK- 40 [min]

(0.5+M)T

CLK + 10 [min]

AVWL

Address (mux’ed) Valid to WR# Low

(1+M)T

CLK- 40 [min]

(0.5+M)T

CLK + 10 [min]

AVWL

Address (demux’ed) Valid to WR# Low

(1+M)T

CLK- 17 [min]

(1+M)T

CLK + 10 [min]

Table 21. 8

x930Ax3 and 8x930Ax4 Real-time Wait State AC Timing Specifications

Symbol (Parameter)

CLK Variable

Default Data Float Timing (ns)

(EDF#=1)

CLK Variable

Extended Data Float Timing (ns)

(EDF#=0)

Min

Typ

Max

Min

Typ

Max

RLYV (PSEN# or RD# Low to

Wait Setup)

00.5 T

CLK - 13

0.5 T

CLK - 35

WLYV (WR# Low to Wait Setup)

0.5 T

CLK - 13

0.5 T

CLK - 35

Table 20. 8

x930Ax3 and 8x930Ax4 Default and Extended Data Float Timings (Continued)

Sym-

bol

Parameter

Default Data Float

Timing (ns)

Compatibility Mode

(EDF# =1) (1,2,4,5)

Extended Data Float

Timing (ns)

Increased T

RHDZ

1 mode

(EDF#=0) (1,3,4,5)

NOTES:

Worst-case numbers based on silicon data collected to date.

Device configured with default data float timing for fast memory interface.

Device configured with extended data float timing for slow memory interface.

The values listed are for 12 MHz. For 6 MHz, the value of T

CLK will double and will equal 166.6 ns.

M=0,1 is the extended ALE state; N= 0,1,2,3 is the RD#/PSEN#/WR# wait state.

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