AD7853_15 datasheet(5/34 Pages) AD

5 / 34 page

REV. B

–5–

AD7853/AD7853L

TYPICAL TIMING DIAGRAMS

Figures 2 and 3 show typical read and write timing diagrams.

Figure 2 shows the reading and writing after conversion in In-

terface Modes 2 and 3. To attain the maximum sample rate of

100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes

2 and 3, reading and writing must be performed during conver-

sion. Figure 3 shows the timing diagram for Interface Modes 4

and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz

(AD7853). At least 400 ns acquisition time must be allowed

(the time from the falling edge of BUSY to the next rising edge

CONVST) before the next conversion begins to ensure that

the part is settled to the 12-bit level. If the user does not want to

provide the

CONVST signal, the conversion can be initiated in

software by writing to the control register.

TO OUTPUT

+2.1V

IOH

1.6mA

200 A

IOL

100pF

Figure 1. Load Circuit for Digital Output Timing

Specifications

POLARITY PIN LOGIC HIGH

SYNC (I/P)

SCLK (I/P)

BUSY (O/P)

CONVST (I/P)

DOUT (O/P)

DB0

DB11

DB15

DB0

THREE-

STATE

DB11

THREE-

STATE

DB15

CONVERT

CONVERT = 4.6 s MAX, 10 s FOR L VERSION

1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V

Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)

POLARITY PIN LOGIC HIGH

SYNC (O/P)

DOUT (O/P)

SCLK (O/P)

DB0

DB11

DIN (I/P)

DB15

DB0

THREE-

STATE

BUSY (O/P)

CONVST (I/P)

DB11

THREE-

STATE

DB15

CONVERT

CONVERT = 4.6 s MAX, 10 s FOR L VERSION

1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V

Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)

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