R5F363AMNFA datasheet(98/119 Pages) RENESAS

98 / 119 page

R01DS0033EJ0220 Rev.2.20

Page 98 of 115

Nov 01, 2012

M16C/63 Group

5. Electrical Characteristics

Figure 5.32

Timing Diagram

BCLK

CSi

ADi

ALE

Hi-Z

DBi

BHE

Read timing

BCLK

CSi

ADi

ALE

BHE

DBi

Write timing

Hi-Z

Memory Expansion Mode and Microprocessor Mode

(in 1 to 3 waits setting and when accessing external area)

= V

= 3V

CC1

CC2

td(BCLK-CS)

30ns(max.)

0ns(min.)

tcyc

th(BCLK-AD)

td(BCLK-AD)

30ns(max.)

td(BCLK-ALE)

25ns(max.)

0ns(min.)

th(BCLK-CS)

-4ns(min.)

th(BCLK-ALE)

0ns(min.)

th(RD-AD)

td(BCLK-RD)

30ns(max.)

0ns(min.)

th(BCLK-RD)

tsu(DB-RD)

0ns(min.)

th(RD-DB)

td(BCLK-CS)

30ns(max.)

0ns(min.)

th(BCLK-CS)

tcyc

td(BCLK-AD)

30ns(max.)

0ns(min.)

th(BCLK-AD)

td(BCLK-ALE)

25ns(max.)

-4ns(min.)

th(BCLK-ALE)

(0.5 × t

-10)ns(min.)

cyc

th(WR-AD)

td(BCLK-WR)

30ns(max.)

0ns(min.)

th(BCLK-WR)

td(BCLK-DB)

40ns(max.)

0ns(min.)

th(WR-DB)

td(DB-WR)

{(n-0.5) × t

-40}ns(min.)

cyc

(0.5 × t

-10)ns(min.)

cyc

th(BCLK-DB)

n: 1 (when 1 wait)

2 (when 2 waits)

3 (when 3 waits)

Measuring conditions

= V

= 3V

CC1

CC2

Input timing voltage: V = 0.6 V, V

= 2.4 V

Output timing voltage: V

= 1.5 V, V

= 1.5 V

f(BCLK)

{(n+0.5) × t

-60}ns(max.)

cyc

tac2(RD-DB)

50ns(min.)

WR, WRL,

WRH

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