OS21, ARM

Board support packages

8083358

9/14

4.2.2

Interrupt table

The interrupt table describes the interrupt system to the OS21 platform-specific interrupt

API implementation code. On ARM there is only one interrupt table. The format of the table

depends upon whether or not interrupt priority levels are supported.

Interrupt table - no interrupt priority level support

Some ARM platforms do not support interrupt levels (for example, STn8815). In this case

each entry in the interrupt table has four fields, as follows:

/* An entry in the interrupt table */

typedef struct interrupt_table_entry_s

{

interrupt_name_t * namep;

unsigned int

controller;

unsigned int

reg_set;

unsigned int

bit_set;

} interrupt_table_entry_t;

The table describes interrupts that are routed to specific interrupt controllers.

namep

is a pointer to the name of the interrupt. controller specifies the interrupt

controller where the interrupt arrives (only OS21_CTRL_INTC is supported on ARM

platforms). reg_set is the number of the register set to which the interrupt is routed.

Currently interrupts are routed to two registers on the interrupt controller; OS21 numbers

these 0 or 1. bit_set is the bit number within this register.

This table enables OS21 to locate an appropriate bit in the INTC that maps to the named

interrupt. For example:

interrupt_name_t OS21_MY_INTERRUPT = 21;

interrupt_table_entry_t my_interrupt =

{ &OS21_MY_INTERRUPT, OS21_CTRL_INTC, 1, 15 };

This describes an interrupt called OS21_MY_INTERRUPT, which is routed into bit 15 of

register set 1 on the interrupt controller OS21_CTRL_INTC.

interrupt_table_entry_t bsp_interrupt_table [];

This describes the set of interrupts that arrive on the INTC. It comprises a list of

interrupt_table_entry_t

types. For example:

interrupt_table_entry_t bsp_interrupt_table [] =

{

{ &OS21_INTERRUPT_TIMER_0, OS21_CTRL_INTC, 0, 0 },

{ &OS21_INTERRUPT_TIMER_1, OS21_CTRL_INTC, 0, 1 },

{ &OS21_INTERRUPT_TIMER_2, OS21_CTRL_INTC, 0, 2 },

{ &OS21_INTERRUPT_TIMER_3, OS21_CTRL_INTC, 0, 3 }

};

This describes a basic system with four timer interrupts. Real systems are likely to be

different to this.