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UM1545 Scheda tecnica(PDF) 46 Page - STMicroelectronics |
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UM1545 Scheda tecnica(HTML) 46 Page - STMicroelectronics |
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46 / 64 page ![]() Audio processor configuration file UM1545 46/64 Doc ID 023225 Rev 1 Appendix B Audio processor configuration file The following example of a device configuration file has extension .apc. Moving along the text, the registers bank, the coefficients bank and the filters bank, that together comprise the device configuration as described in the introduction of Section 2.1: IntroductionSection 2: APW walkthrough, can be easily identified. ##################################################### # Date: Wednesday, 12/November/'08 # Interface: Simulation (NONE) # Product: STA339BWS ##################################################### ################### FFX registers ################### Reg[00h] = 63h ## Configuration Register A Reg[01h] = 80h ## Configuration Register B Reg[02h] = 97h ## Configuration Register C Reg[03h] = 40h ## Configuration Register D Reg[04h] = C2h ## Configuration Register E Reg[05h] = 5Ch ## Configuration Register F Reg[06h] = 10h ## Master Mute Reg[07h] = FFh ## Master Volume Reg[08h] = 60h ## Channel 1 Volume Reg[09h] = 60h ## Channel 2 Volume Reg[0Ah] = 60h ## Channel 3 Volume Reg[0Bh] = 80h ## Audio Preset Register 1 Reg[0Ch] = 00h ## Audio Preset Register 2 Reg[0Dh] = 00h ## Reserved Reg[0Eh] = 00h ## Channel 1 Config Reg[0Fh] = 40h ## Channel 2 Config Reg[10h] = 80h ## Channel 3 Config Reg[11h] = 77h ## Bass and Treble Tone Control Reg[12h] = 6Ah ## Limiter 1 Attack/Release Rate Reg[13h] = 69h ## Limiter 1 Attack/Release Threshold Reg[14h] = 6Ah ## Limiter 2 Attack/Release Rate Reg[15h] = 69h ## Limiter 2 Attack/Release Threshold Reg[16h] = 00h ## Coefficient Address Bits 5..0 Reg[17h] = 00h ## Coefficient b1 Data Bits 23..16 Reg[18h] = 00h ## Coefficient b1 Data Bits 15..8 Reg[19h] = 00h ## Coefficient b1 Data Bits 7..0 Reg[1Ah] = 00h ## Coefficient b2 Data Bits 23..16 Reg[1Bh] = 00h ## Coefficient b2 Data Bits 15..8 Reg[1Ch] = 00h ## Coefficient b2 Data Bits 7..0 Reg[1Dh] = 00h ## Coefficient a1 Data Bits 23..16 Reg[1Eh] = 00h ## Coefficient a1 Data Bits 15..8 Reg[1Fh] = 00h ## Coefficient a1 Data Bits 7..0 Reg[20h] = 00h ## Coefficient a2 Data Bits 23..16 Reg[21h] = 00h ## Coefficient a2 Data Bits 15..8 Reg[22h] = 00h ## Coefficient a2 Data Bits 7..0 Reg[23h] = 00h ## Coefficient b0 Data Bits 23..16 Reg[24h] = 00h ## Coefficient b0 Data Bits 15..8 Reg[25h] = 00h ## Coefficient b0 Data Bits 7..0 |
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