UPD17708 datasheet(314/356 Pages) NEC

314 / 356 page

314

µPD17704, 17705, 17707, 17708, 17709

21.3.1 Power-ON reset during normal operation

Figure 21-6 (a) shows the operation.

As shown, the power-ON clear signal is output and the device operation is stopped if the supply voltage VDD drops

below 3.5 V, regardless of the input level of the CE pin.

If VDD rises beyond 3.5 V again, program execution starts from address 0000H after a halt of 50 ms.

Normal operation means operation without the clock stop instruction, and includes the halt status set by the halt

instruction.

21.3.2 Power-ON reset in clock stop status

Figure 21-6 (b) shows the operation.

As shown, the power-ON clear signal is output and the device operation is stopped when supply voltage VDD drops

below 2.2 V.

However, it does not appear that device operation has changed because the device is in the clock stop status.

If VDD rises beyond 3.5 V, program execution starts from address 0000H after a halt of 50 ms.

21.3.3 Power-ON reset when supply voltage VDD rises from 0 V

Figure 21-6 (c) shows the operation.

As shown, the power-ON clear signal is output until supply voltage VDD rises from 0 V to 3.5 V.

When VDD exceeds the power-ON clear voltage, the crystal oscillation circuit starts operating, and program execution

starts from address 0000H after a half of 50 ms.

UPD17708 Scheda tecnica(PDF) 314 Page - NEC