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Motore di ricerca datesheet componenti elettronici |
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Motore di ricerca datesheet componenti elettronici |
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UPD17708 Scheda tecnica(PDF) 151 Page - NEC |
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UPD17708 Scheda tecnica(HTML) 151 Page - NEC |
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151 / 356 page  151 µPD17704, 17705, 17707, 17708, 17709 13.2.2 Clock selection block The clock selection block divides the system clock (4.5 MHz) and sets the time interval at which the BTM0CY flag is to be set, by using the BTM0CK0 and BTM0CK1 flags. Figure 13-3 shows the configuration of the basic timer 0 clock selection register. Figure 13-3. Configuration of Basic Timer 0 Clock Selection Register Name Flag symbol b3 0 b2 0 b1 B T M 0 C K 1 b0 B T M 0 C K 0 Address 18H Read/Write R/W Basic timer 0 clock selection Power-ON reset WDT&SP reset CE reset Clock stop 0 1 0 1 0 0 10 Hz (100 ms) 20 Hz (50 ms) 50 Hz (20 ms) 100 Hz (10 ms) Fixed to “0” Sets time interval at which BTM0CY flag is set 00 0 0 1 1 0 0 Retained Retained |
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